1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) which stores “1”- and “0”-data using a magnetoresistive effect.
2. Description of the Related Art
In recent years, many memories which store data by new principles have been proposed. One of them is a magnetic random access memory (MRAM) using a tunneling magnetoresistive (to be referred to as TMR hereinafter) effect. As a proposal for a magnetic random access memory, for example, the following nonpatent reference 1 is known: Roy Scheuerlein et al, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, 2000 ISSCC Digest of Technical Papers (U.S.A.), February 2000, pp. 128-129 is known.
A magnetic random access memory stores “1”- or “0”-data in an MTJ (Magnetic Tunnel Junction) element using the TMR effect for read operation. As the basic structure of an MTJ element, an insulating layer (tunneling barrier) is sandwiched between two magnetic layers (ferromagnetic layers).
Data stored in the MTJ element is determined on the basis of whether the magnetizing states of the two magnetic layers are parallel or antiparallel. “Parallel” means that the two magnetic layers have the same magnetizing direction. “Antiparallel” means that the two magnetic layers have opposite magnetizing directions.
When the magnetized state of the MTJ element is “parallel”, the tunneling resistance of the insulating layer (tunneling barrier layer) sandwiched between the two magnetic layers of the MTJ element is minimized. For example, this state is defined as a “1”-state. When the magnetized state of the MTJ element is “antiparallel”, the tunneling resistance of the insulating layer (tunneling barrier layer) sandwiched between the two magnetic layers of the MTJ element is maximized. For example, this state is defined as a “0”-state.
Currently, various kinds of cell array structures have been examined for a magnetic random access memory from the viewpoint of increasing the memory capacity or stabilizing write/read operation.
For example, currently, a cell array structure in which one memory cell is formed from one MOS transistor and one MTJ element is known. Additionally, a magnetic random access memory which has such a cell array structure and stores 1-bit data using two memory cells so as to implement stable read operation is also known.
However, in these magnetic random access memories, it is difficult to increase the memory capacity. This is because one MOS transistor corresponds to one MTJ element in these cell array structures.
For example, array structures in which a plurality of MTJ elements are connected in parallel have been proposed (e.g., patent reference 1 (Japanese Patent Application No. 2000-296082) and patent reference 2 (Japanese Patent Application No. 2001-350013)). According to these cell array structures, since one MOS transistor corresponds to a plurality of MTJ elements, the memory capacity can be increased as compared to the cell array structure having memory cells each formed from one MTJ element and one MOS transistor.
In the techniques disclosed in patent references 1 and 2, however, the MTJ elements are two-dimensionally arranged in one plane. For this reason, the integration density of MTJ elements cannot be sufficiently increased.
To solve this problem, a technique for three-dimensionally arranging MTJ elements on a semiconductor substrate has been proposed. More specifically, in this technique, a plurality of MTJ elements connected in series or parallel are arranged in correspondence with one MOS transistor (select transistor) formed in the surface region of a semiconductor substrate. In addition, the plurality of MTJ elements are stacked in a plurality of stages on one MOS transistor.
This technique is disclosed in detail in, e.g., patent reference 3 (Japanese Patent Application No. 2001-365236). According to this technique, a plurality of MTJ elements are stacked in a plurality of stages on one MOS transistor. This is convenient for increasing the memory capacity of the memory cell array.
In the techniques disclosed in patent references 1 and 2, a so-called destructive read operation principle is applied to read operation. As described in detail in these references, the destructive read operation principle has a problem that since read operation of one cycle basically comprises two read steps and two write steps, the read time is long.
To the contrary, in the technique disclosed in patent reference 3, the plurality of MTJ elements connected in series or parallel in a block have different resistance ratios. Hence, data of the plurality of MTJ elements in the block can be read out simultaneously by only one read step.
In the technique disclosed in patent reference 3, however, since the plurality of MTJ elements connected in series or parallel in a block must have different resistance ratios, the structure and manufacturing method of an MTJ element are complex. Additionally, since read data contains the data of the plurality of MTJ elements, an A/D conversion circuit or logic circuit which extracts the data of each MTJ element from the read data is necessary, resulting in a complex read circuit.
Still another example is a magnetic random access memory having a circuit structure as shown in FIG. 46 (e.g., patent reference 4 (Japanese Patent Application No. 2001-390549) and patent reference 5 (Japanese Patent Application No. 2001-390518)).
In a magnetic random access memory with such a circuit structure, assume that four MTJ elements (MTJ1, MTJ2, MTJ3, and MTJ4) 12 selected by a read word line RWL1 in, e.g., a lower left block BK11 are to be simultaneously read-accessed. The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 form two complementary pairs.
In this circuit structure, assume that the same potential is biased to bit lines BL1, BL2, BL3, and BL4. In this case, the MTJ elements 12 in an unselected lower right block BLj1 make current paths between the bit lines BL1, BL2, BL3, and BL4. But no current flows between the bit lines BL1, BL2, BL3, and BL4, because their potentials are same. Hence, currents (solid lines) flowing to the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the selected lower left block BK11 are read out by sense amplifiers 15-1, 15-2, 15-3, and 15-4, respectively.
However, if a potential difference is generated, a current flows through the MTJ elements 12 in an unselected lower right block BLj1. As the number of MTJ elements connected to each of the bit lines BL1, BL2, BL3, and BL4 increases, the current becomes large.
A select cell MOS transistor (column select switch 14-1) is inserted between the common line to the sense amplifiers 15-1, 15-2, 15-3, and 15-4 and the bit lines BL1, BL2, BL3, and BL4. Since the select MOS transistor has a resistance, a potential difference is generated in accordance with the resistance of the selected MTJ element. When the potential difference is generated between the bit lines BL1, BL2, BL3, and BL4, a current flows through the common node of the MTJ elements in the block.
For descriptive convenience, assume that the MTJ elements connected to the bit lines BL1, BL2, BL3, and BL4 have the same resistance value, only the MTJ element connected to the bit line BL1 is in a high-resistance state (the magnetizing directions of the storing layer and fixed layer are antiparallel), and the MTJ elements connected to the remaining bit lines BL2, BL3, and BL4 are in a low-resistance state (the magnetizing directions of the storing layer and fixed layer are parallel).
Let Is be the signal current difference when the MTJ elements are in the high- and low-resistance states, V be the bias voltage from the sense amplifier, Rm be the resistance of the MTJ element, Rt be the resistance of the MOS transistor of the block select switch, and Rc be the resistance of the MOS transistor of the column select switch. The signal current difference Is is given byIs=V/(Rt+Rc+Rm)−V/[Rt+Rc+Rm·(1+MR)]=MR×V/Rm÷[1+(Rt+Rc)/Rm]+[1+MR+(Rt+Rc)/Rm]  (1)
A potential difference V between the bit line BL1 and the bit lines BL2, BL3, and BL4 due to the resistance of the MTJ element and that of the MOS transistor by data is given by                               ⁢          V                =                                                            V                /                                  [                                      Rt                    +                    Rc                    +                                          Rm                      ·                                              (                                                  1                          +                          MR                                                )                                                                              ]                                            ×                              [                                  Rt                  +                                      Rm                    ·                                          (                                              1                        +                        MR                                            )                                                                      ]                                      -                                          V                /                                  [                                      Rt                    +                    Rc                    +                    Rm                                    ]                                            ×                              [                                  Rt                  +                  Rm                                ]                                              =                      MR            ×            V            ×                                                            Rc                  /                  Rm                                ÷                                  [                                      1                    +                                                                  (                                                  Rt                          +                          Rc                                                )                                            /                      Rm                                                        ]                                            ÷                              [                                  1                  +                  MR                  +                                                            (                                              Rt                        +                        Rc                                            )                                        /                    Rm                                                  ]                                                                        (        2        )            
Let n be the number of MTJ elements connected to a bit line BL. Then, a current
(three dotted lines in FIG. 46) which flows in a direction to cancel the signal current difference Is through the common terminal of the MTJ elements flows through a synthesized resistance in which the synthesized resistance of the three MTJ elements MTJ2, MTJ3, and MTJ4 arrayed in parallel and one MTJ element MTJ1 is in a n−1 parallel state. Hence, the currentis given by                               ⁢          I                =                              ⁢                          V              ⁡                              [                                                      (                                          Rm                      +                                              Rm                        /                        3                                                              )                                    /                                      (                                          n                      -                      1                                        )                                                  ]                                              ⁢                                          ⁢                                           =                      V            ×                                          (                                  n                  -                  1                                )                            /                              (                                  4                  ·                                      Rm                    /                    3                                                  )                                      ×                          Rc              /              Rm                        ×                                          MR                ÷                                                                  ⁢                                                                   ⁢                                  [                                      1                    +                                                                  (                                                  Rt                          +                          Rc                                                )                                            /                      Rm                                                        ]                                            ÷                              [                                  1                  +                  MR                  +                                                            (                                              Rt                        +                        Rc                                            )                                        /                    Rm                                                  ]                                                                        (        3        )            
From equations (1) to (3), the net signal current difference Is′ is given by                               Is          ′                =                              Is            -                          ⁢              I                                ⁢                                          ⁢                                           =                      MR            ×                                          V                /                Rm                            ÷                                                                                                           [                                              1                        +                                                                              (                                                          Rt                              +                              Rc                                                        )                                                    /                          Rm                                                                    ]                                        ÷                                                                                  ⁢                                                                                   ⁢                                          [                                              1                        +                        MR                        +                                                                              (                                                          Rt                              +                              Rc                                                        )                                                    /                          Rm                                                                    ]                                                        ×                                      [                                          1                      -                                              Rc                        ·                                                                              (                                                          n                              -                              1                                                        )                                                    /                                                      (                                                          4                              ·                                                              Rm                                /                                3                                                                                      )                                                                                                                ]                                                                                                          (        4        )            
In equation (4), if the relationship 1−Rc·(n−1)/(4·Rm/3)>0, i.e., Rm/Rc>4(n−1)/3 is not satisfied, a read error occurs.
To prevent the read error, the resistance Rm of the MTJ element must be increased, the channel width of the MOS transistor of the column select switch must be increased, or the number of cells connected to the bit line BL must be decreased.
However, if the number of cell arrays is simply increased while decreasing the number of cells connected to the bit line BL due to the constraint on the maximum number of cells connectable to the bit line BL, the chip size increases, and it may be impossible to sufficiently increase the integration density of MTJ elements. For this reason, the above measures can hardly be taken for a large-capacity memory.